Layout Verification System LAYVER

  The Layout Verification System LAYVER provides the user with tools to:

• check an IC layout design with respect to technological design rules (DRC).

• extract the realized (on chip) circuit and compare it with the desired circuit (LVS).

• extract both intended and parasitic devices as a net-list for accurate simulation (LPE)

• identify electrical inconsistencies and abnormalities in the layout (ERC)

• carry out other database massaging, for example, layer generation

A number of different types of commands are required to solve these problems:

• derive new layers by shrinking or bloating a layer or perform logical operations on layers.

• device recognition – certain layers when related in a manner defined by the command file may be identified as a device

• calculate physical and electrical parameters that depend on the geometry of drawn regions and set minimum and maximum check limits to these parameters for the LVS.

• For evaluation of LAYVER results the IC Layout Editor LAYED is provided.

Program Components and Features:

• Data read-in
  LAYVER expects primary data to be stored in TexEDA's graphical DBX format. After resolving group hierarchy starting from a user-definable main group LAYVER stores the result in the LAYVER database in segmented regions not overlapping each other.
  Where the layout is presented in GDS2 format, an internationally accepted standard for graphical layout, a conversion to the proprietary DBX format must be performed before LAYVER can process the data. Tools for both GDS2 to DBX and DBX to GDS2 conversion are included as part of the LAYVER package.
     TOP

• Layer operations
  New layers can be created by bloating or shrinking a layer or by logical operations on layers. This facilitates the circuit extraction for a LVS check and the DRC for very complex design rules. These functions are also used to adapt the design to special technology demands.
  LAYVER offers a large variety of layer operations, including region, text and edge operations. Design Rule Checks are special edge operations with results that may be used in further layer operations.
  The special DRC option "/REGION" support the Parasitics Extraction
     TOP

• The DRC
  LAYVER provides the user with versatile Design Rule Check functions and filters. The relative position of sides within one region, or the relative position of sides of one region with respect to another in the same or a different layer, may be checked against technology design rules provided by the semiconductor vendor. Associated requirements including local or global coverage calculation, antenna checks, and latch-up checks may also be made.
     TOP

• Circuit extraction
   In order to compare the realized and desired circuits, LAYVER has to extract the realized electrical circuit from the layout. Any uniquely definable structure may be extracted as a device. Having carried out an extraction and prior to comparison, the user may combine several devices in the extracted circuit to one device (e.g. resistors networks to one resistor, multi-fingered transistors to one device, transistors to gates, etc.). The approach to combining devices is user-controllable. It is also possible to remove (filter) unused devices from the extracted circuit in order to facilitate the LVS of such circuits as gate-arrays.
  The extracted circuit can be converted into netlists of various formats (e.g. PSpice, HSpice). This makes the realized circuit available for the most common simulation programs.
      TOP

• Parameter and Parasitics calculation
  LAYVER calculates geometrical and electrical parameters of extracted devices using user-definable expressions. Furthermore, for the nodes in a circuit it provides the possibility to calculate parameters that depend on the geometry of conducting regions and on the parameters of connected devices.
      TOP

• Circuit comparison
  (LVS)
   The Layout Versus Schematic (LVS) check finds out as many references as possible between the extracted and the desired circuit. Remaining differences caused by design errors can be precisely localized using LAYED.
  To improve the performance of the LVS check the user can put labels on nodes or devices in the layout to reference them in the desired circuit. The circuit comparison includes also the checking of extracted and calculated parameters with respect to their values in the desired circuit. Parameter tolerances can be defined.
      TOP
  
  (SVS)
  The Schematic Versus Schematic (SVS) check compares two netlists generated by different design systems.
     TOP

• Plots integrated in LAYVER
  A universal driver converts a drawing into a compressed vector file. This file can be further processed by printer/plotter dependent drivers. A plotter program (LAYPLOT) for WINDOWS-GDI supported printers/plotters is optionally available from TexEDA Design. Another way is to use the graphics editor LAYED for plotting layers or LAYVER results via the PRINT command.
     TOP

• Data exchange utilities
  LAYVER comes with a number of utilities to convert one data format to the other, e. g. from the internal LAYVER data format to DBX and from DBX to GDS2, CALTECH CIF, AUTOCAD DXF(2D) and GERBER(RS-274X) and vice versa. Additional utilities convert several netlist formats, e. g. the XNDL format used by LAYVER to HSpice or PSpice and back.
     TOP

BACK

Copyright (C) TexEDA Design GmbH