SPE/LAYCIR (Schematic & Probing Environment)

SPE is a schematic capture package developed for entering the schematics of integrated electronic circuits.
LAYCIR is a new version of SPE used in LAYFRAME, moreover new interfaces support the Simulation with SIMetrix, Smash, and ADS

Features:

• SPE creates and processes  schematic graphical data in a hierarchical structured form

• SPE is unlimited to the number of hierarchical level for a schematic

• Free navigation in hierarchy from the schematic view is possible

• SPE supports the following data elements: symbols, schematic elements, attributes, text, buses, bus taps, pins, and wires (nets)

• Free customization of symbols is possible, both primitive devices (such as transistors, resistors, and gates) and complex sub-circuits referred to as "block" symbols

• SPE uses attributes to describe the characteristics or properties of symbols and pins

• SPE supports the establishment of reference directories for symbol files

• Flexible naming of instances, nets, and buses is possible

• SPE uses an open ASCII format for schematic files so that data can be converted to and from a number of standard formats

• The SPE-Netlister generates netlists that may be used directly for simulation (for example, using PSpice or HSpice), for automatic layout generation (using Place & Route such as LAYPAR from TexEDA Design GmbH), or for layout verification (for example, using LAYVER also from TexEDA)

• Template-driven netlist generation available

• Cross-probing can be carried out together with tool LAYED (for LAYVER evaluation or layout editing in SDLE-mode)

• SPE checks the schematic consistency (connectivity checking)

• Callback parameter calculation using LAYED pGroup procedures

• Back annotation for simulation results is possible (SMASH results)

• The SPE input file may be an ECS-Synario ASCII file

• The SPE-SIMetrix Interface (SLI) provides the following capabilities:

  • Choosing analysis from SPE

  • Creating a SIMetrix compatible netlist (SPICE format) from a SPE schematic

  • Starting the simulation from SPE

  • Post-probing of node voltages and device port currents from SPE

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